The present invention relates to a semiconductor integrated circuit and a method of operating a semiconductor integrated circuit and for example, to a semiconductor integrated circuit that mounts a logic circuit having a computing mode and a sleep mode and a method of operating such a semiconductor integrated circuit.
In order to realize a reduction in power consumption of a semiconductor integrated circuit, semiconductor integrated circuits having applied the DVS (Dynamic Voltage Scaling) technique or the AVS (Adaptive Voltage Scaling) technique are becoming widespread (for example, see U.S. Pat. No. 5,745,375 (Patent Document 1), Japanese Patent Laid-Open No. 2009-200739 (Patent Document 2), Japanese Patent Laid-Open No. 2011-119609 (Patent Document 3), and Japanese Patent Laid-Open No. 2005-250736 (Patent Document 4)).
Patent Document 1 describes a technique relating to a power source control device circuit for reducing power consumption by electronic equipment. The power source control device circuit includes a control device, a clock generation circuit, and a power source circuit. The control device is a power source circuit managed by power management software and the clock generation circuit sets voltage and frequency in accordance with two different states.
Patent Document 2 describes a technique relating to a semiconductor integrated circuit implementing the AVS technique or the DVS technique suitable to a reduction in power consumption. The semiconductor integrated circuit forms a critical path by a first flip-flop, a combination circuit, and a second flip-flop. Furthermore, in the subsequent stage of the combinational circuit, a first delay circuit and a third flip-flop are provided. Similarly, in the subsequent state of the combination circuit, a second delay circuit and a fourth flip-flop are provided. Moreover, there are provided a first comparison circuit that compares the output of the second flip-flop and the output of the third flip-flop, a second comparison circuit that compares the output of the second flip-flop and the output of the fourth flip-flop, and a control circuit that controls a power source voltage to be supplied to the combination circuit in accordance with the outputs of these comparison circuits.
Patent Document 3 describes a technique relating to stabilization of a plurality of power source voltages. Patent Document 4 describes a technique relating to a power control device capable of shortening the transition time when switching power source voltages. The power control device includes a processor chip and a power source voltage generation device that generates variable power source voltages to be supplied to the processor chip. Furthermore, the processor chip includes a power source voltage determination device that selects one of the power source voltages generated by the power source voltage generation device.